ISSDK  1.8
IoT Sensing Software Development Kit
fxls896x.h
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1 /*
2  * Copyright 2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 /**
8  * @file fxls896x.h
9  * @brief This file contains the FXLS896XAF Accelerometer register definitions, access macros, and
10  * device access functions.
11  */
12 #ifndef FXLS896X_H_
13 #define FXLS896X_H_
14 #include <stddef.h>
15 #include <stdint.h>
16 #include <stdbool.h>
17 /**
18  * @brief The FXLS896x types
19  */
20 
21 /**
22  **
23  ** @brief The FXLS896x Sensor Internal Register Map.
24  */
25 enum
26 {
27  FXLS896x_INT_STATUS = 0x00,
28  FXLS896x_TEMP_OUT = 0x01,
29  FXLS896x_VECM_LSB = 0x02,
30  FXLS896x_VECM_MSB = 0x03,
31  FXLS896x_OUT_X_LSB = 0x04,
32  FXLS896x_OUT_X_MSB = 0x05,
33  FXLS896x_OUT_Y_LSB = 0x06,
34  FXLS896x_OUT_Y_MSB = 0x07,
35  FXLS896x_OUT_Z_LSB = 0x08,
36  FXLS896x_OUT_Z_MSB = 0x09,
37  FXLS896x_BUF_STATUS = 0x0B,
38  FXLS896x_BUF_X_LSB = 0x0C,
39  FXLS896x_BUF_X_MSB = 0x0D,
40  FXLS896x_BUF_Y_LSB = 0x0E,
41  FXLS896x_BUF_Y_MSB = 0x0F,
42  FXLS896x_BUF_Z_LSB = 0x10,
43  FXLS896x_BUF_Z_MSB = 0x11,
44  FXLS896x_PROD_REV = 0x12,
45  FXLS896x_WHO_AM_I = 0x13,
46  FXLS896x_SYS_MODE = 0x14,
47  FXLS896x_SENS_CONFIG1 = 0x15,
48  FXLS896x_SENS_CONFIG2 = 0x16,
49  FXLS896x_SENS_CONFIG3 = 0x17,
50  FXLS896x_SENS_CONFIG4 = 0x18,
51  FXLS896x_SENS_CONFIG5 = 0x19,
52  FXLS896x_WAKE_IDLE_LSB = 0x1A,
53  FXLS896x_WAKE_IDLE_MSB = 0x1B,
54  FXLS896x_SLEEP_IDLE_LSB = 0x1C,
55  FXLS896x_SLEEP_IDLE_MSB = 0x1D,
56  FXLS896x_ASLP_COUNT_LSB = 0x1E,
57  FXLS896x_ASLP_COUNT_MSB = 0x1F,
58  FXLS896x_INT_EN = 0x20,
59  FXLS896x_INT_PIN_SEL = 0x21,
60  FXLS896x_OFF_X = 0x22,
61  FXLS896x_OFF_Y = 0x23,
62  FXLS896x_OFF_Z = 0x24,
63  FXLS896x_BUF_CONFIG1 = 0x26,
64  FXLS896x_BUF_CONFIG2 = 0x27,
65  FXLS896x_ORIENT_STATUS = 0x28,
66  FXLS896x_ORIENT_CONFIG = 0x29,
67  FXLS896x_ORIENT_DBCOUNT = 0x2A,
68  FXLS896x_ORIENT_BF_ZCOMP = 0x2B,
69  FXLS896x_ORIENT_THS_REG = 0x2C,
70  FXLS896x_SDCD_INT_SRC1 = 0x2D,
71  FXLS896x_SDCD_INT_SRC2 = 0x2E,
72  FXLS896x_SDCD_CONFIG1 = 0x2F,
73  FXLS896x_SDCD_CONFIG2 = 0x30,
74  FXLS896x_SDCD_OT_DBCNT = 0x31,
75  FXLS896x_SDCD_WT_DBCNT = 0x32,
76  FXLS896x_SDCD_LTHS_LSB = 0x33,
77  FXLS896x_SDCD_LTHS_MSB = 0x34,
78  FXLS896x_SDCD_UTHS_LSB = 0x35,
79  FXLS896x_SDCD_UTHS_MSB = 0x36,
80  FXLS896x_SELF_TEST_CONFIG1 = 0x37,
81  FXLS896x_SELF_TEST_CONFIG2 = 0x38,
82 };
83 
84 #define FXLS896x_DEVICE_ADDRESS_SA0_0 (0x18) /*!< Device Address Value. */
85 #define FXLS896x_DEVICE_ADDRESS_SA0_1 (0x19) /*!< Device Address Value. */
86 #define FXLS896x_WHOAMI_VALUE (0x62) /*!< Who AM I Value. */
87 #define FXLS8964_WHOAMI_VALUE (0x84) /*!< Who AM I Value.of FXLS8964AF */
88 #define FXLS8967_WHOAMI_VALUE (0x87) /*!< Who AM I Value.of FXLS8967AF */
89 #define FXLS8974_WHOAMI_VALUE (0x86) /*!< Who AM I Value.of FXLS8974CF */
90 #define FXLS896x_TBOOT_MAX 20 /*!< Maximum safe value for TBOOT1/2 in ms (1ms, 17.7ms)=~20ms. */
91 
92 /*--------------------------------
93 ** Register: INT_STATUS
94 ** Enum: FXLS896x_INT_STATUS
95 ** --
96 ** Offset : 0x00 Interrupt and system status event flags.
97 ** ------------------------------*/
98 typedef union
99 {
100  struct
101  {
102  uint8_t src_boot : 1; /* System boot complete event flag. */
103 
104  uint8_t src_aslp : 1; /* Auto-Wake/Sleep event status flag. */
105 
106  uint8_t src_orient : 1; /* Orientation change event flag. */
107 
108  uint8_t src_sdcd_wt : 1; /* SDCD within thresholds condition event flag. */
109 
110  uint8_t src_sdcd_ot : 1; /* SDCD outside of threshold condition event flag. */
111 
112  uint8_t src_buf : 1;/* Output data buffer status event flag. */
113 
114  uint8_t src_ovf : 1; /* Output data overflow event flag. */
115 
116  uint8_t src_drdy : 1; /* Output data ready event flag. */
117 
118  } b;
119  uint8_t w;
120 } FXLS896x_INT_STATUS_t;
121 
122 /*
123 ** INT_STATUS - Bit field mask definitions
124 */
125 #define FXLS896x_INT_STATUS_SRC_BOOT_MASK ((uint8_t)0x01)
126 #define FXLS896x_INT_STATUS_SRC_BOOT_SHIFT ((uint8_t)0)
127 
128 #define FXLS896x_INT_STATUS_SRC_ASLP_MASK ((uint8_t)0x02)
129 #define FXLS896x_INT_STATUS_SRC_ASLP_SHIFT ((uint8_t)1)
130 
131 #define FXLS896x_INT_STATUS_SRC_ORIENT_MASK ((uint8_t)0x04)
132 #define FXLS896x_INT_STATUS_SRC_ORIENT_SHIFT ((uint8_t)2)
133 
134 #define FXLS896x_INT_STATUS_SRC_SDCD_WT_MASK ((uint8_t)0x08)
135 #define FXLS896x_INT_STATUS_SRC_SDCD_WT_SHIFT ((uint8_t)3)
136 
137 #define FXLS896x_INT_STATUS_SRC_SDCD_OT_MASK ((uint8_t)0x10)
138 #define FXLS896x_INT_STATUS_SRC_SDCD_OT_SHIFT ((uint8_t)4)
139 
140 #define FXLS896x_INT_STATUS_SRC_BUF_MASK ((uint8_t)0x20)
141 #define FXLS896x_INT_STATUS_SRC_BUF_SHIFT ((uint8_t)5)
142 
143 #define FXLS896x_INT_STATUS_SRC_OVF_MASK ((uint8_t)0x40)
144 #define FXLS896x_INT_STATUS_SRC_OVF_SHIFT ((uint8_t)6)
145 
146 #define FXLS896x_INT_STATUS_SRC_DRDY_MASK ((uint8_t)0x80)
147 #define FXLS896x_INT_STATUS_SRC_DRDY_SHIFT ((uint8_t)7)
148 
149 /*------------------------------*/
150 
151 /*--------------------------------
152 ** Register: TEMP_OUT
153 ** Enum: FXLS896x_TEMP_OUT
154 ** --
155 ** Offset : 0x01 Temperature output data.
156 ** ------------------------------*/
157 typedef uint8_t FXLS896x_TEMP_OUT_t;
158 
159 /*--------------------------------
160 ** Register: VECM_LSB
161 ** Enum: FXLS896x_VECM_LSB
162 ** --
163 ** Offset : 0x02 12-bit unsigned vector magnitude LSB.
164 ** ------------------------------*/
165 typedef uint8_t FXLS896x_VECM_LSB_t;
166 
167 /*--------------------------------
168 ** Register: VECM_MSB
169 ** Enum: FXLS896x_VECM_MSB
170 ** --
171 ** Offset : 0x03 12-bit unsigned vector magnitude MSB.
172 ** ------------------------------*/
173 typedef uint8_t FXLS896x_VECM_MSB_t;
174 
175 /*--------------------------------
176 ** Register: OUT_X_LSB
177 ** Enum: FXLS896x_OUT_X_LSB
178 ** --
179 ** Offset : 0x04 LSB of current 12-bit X-axis accelerometer output data.
180 ** ------------------------------*/
181 typedef uint8_t FXLS896x_OUT_X_LSB_t;
182 
183 /*--------------------------------
184 ** Register: OUT_X_MSB
185 ** Enum: FXLS896x_OUT_X_MSB
186 ** --
187 ** Offset : 0x05 MSB of current 12-bit X-axis accelerometer output data.
188 ** ------------------------------*/
189 typedef uint8_t FXLS896x_OUT_X_MSB_t;
190 
191 /*--------------------------------
192 ** Register: OUT_Y_LSB
193 ** Enum: FXLS896x_OUT_Y_LSB
194 ** --
195 ** Offset : 0x06 LSB of current 12-bit Y-axis accelerometer output data.
196 ** ------------------------------*/
197 typedef uint8_t FXLS896x_OUT_Y_LSB_t;
198 
199 /*--------------------------------
200 ** Register: OUT_Y_MSB
201 ** Enum: FXLS896x_OUT_Y_MSB
202 ** --
203 ** Offset : 0x07 MSB of current 12-bit Y-axis accelerometer output data.
204 ** ------------------------------*/
205 typedef uint8_t FXLS896x_OUT_Y_MSB_t;
206 
207 /*--------------------------------
208 ** Register: OUT_Z_LSB
209 ** Enum: FXLS896x_OUT_Z_LSB
210 ** --
211 ** Offset : 0x08 LSB of current 12-bit Z-axis accelerometer output data.
212 ** ------------------------------*/
213 typedef uint8_t FXLS896x_OUT_Z_LSB_t;
214 
215 /*--------------------------------
216 ** Register: OUT_Z_MSB
217 ** Enum: FXLS896x_OUT_Z_MSB
218 ** --
219 ** Offset : 0x09 MSB of current 12-bit Z-axis accelerometer output data.
220 ** ------------------------------*/
221 typedef uint8_t FXLS896x_OUT_Z_MSB_t;
222 
223 /*--------------------------------
224 ** Register: BUF_STATUS
225 ** Enum: FXLS896x_BUF_STATUS
226 ** --
227 ** Offset : 0x0B Buf status.
228 ** ------------------------------*/
229 typedef union {
230  struct {
231  uint8_t buf_cnt : 6; /* Count of the acceleration data samples */
232 
233  uint8_t buf_ovf : 1; /* Buffer Overflow Event Flag */
234 
235  uint8_t buf_wmrk : 1; /* Buffer Watermark Event Flag */
236 
237  } b;
238  uint8_t w;
239 } FXLS896x_BUF_STATUS_t;
240 
241 
242 /*
243 ** BUF_STATUS - Bit field mask definitions
244 */
245 #define FXLS896x_BUF_STATUS_BUF_CNT_MASK ((uint8_t) 0x3F)
246 #define FXLS896x_BUF_STATUS_BUF_CNT_SHIFT ((uint8_t) 0)
247 
248 #define FXLS896x_BUF_STATUS_BUF_OVF_MASK ((uint8_t) 0x40)
249 #define FXLS896x_BUF_STATUS_BUF_OVF_SHIFT ((uint8_t) 6)
250 
251 #define FXLS896x_BUF_STATUS_BUF_WMRK_MASK ((uint8_t) 0x80)
252 #define FXLS896x_BUF_STATUS_BUF_WMRK_SHIFT ((uint8_t) 7)
253 
254 
255 
256 /*--------------------------------
257 ** Register: BUF_X_LSB
258 ** Enum: FXLS896x_BUF_X_LSB
259 ** --
260 ** Offset : 0x0C LSB Head Tail output buffer buffer X axis.
261 ** ------------------------------*/
262 typedef uint8_t FXLS896x_BUF_X_LSB_t;
263 
264 
265 /*--------------------------------
266 ** Register: BUF_X_MSB
267 ** Enum: FXLS896x_BUF_X_MSB
268 ** --
269 ** Offset : 0x0D MSB Head Tail output buffer buffer Z axis.
270 ** ------------------------------*/
271 typedef uint8_t FXLS896x_BUF_X_MSB_t;
272 
273 
274 /*--------------------------------
275 ** Register: BUF_Y_LSB
276 ** Enum: FXLS896x_BUF_Y_LSB
277 ** --
278 ** Offset : 0x0E LSB Head Tail output buffer buffer Y axis.
279 ** ------------------------------*/
280 typedef uint8_t FXLS896x_BUF_Y_LSB_t;
281 
282 
283 /*--------------------------------
284 ** Register: BUF_Y_MSB
285 ** Enum: FXLS896x_BUF_Y_MSB
286 ** --
287 ** Offset : 0x0F MSB Head Tail output buffer buffer Y axis.
288 ** ------------------------------*/
289 typedef uint8_t FXLS896x_BUF_Y_MSB_t;
290 
291 
292 /*--------------------------------
293 ** Register: BUF_Z_LSB
294 ** Enum: FXLS896x_BUF_Z_LSB
295 ** --
296 ** Offset : 0x10 LSB Head Tail output buffer buffer Z axis.
297 ** ------------------------------*/
298 typedef uint8_t FXLS896x_BUF_Z_LSB_t;
299 
300 
301 /*--------------------------------
302 ** Register: BUF_Z_MSB
303 ** Enum: FXLS896x_BUF_Z_MSB
304 ** --
305 ** Offset : 0x11 MSB Head Tail output buffer buffer Z axis.
306 ** ------------------------------*/
307 typedef uint8_t FXLS896x_BUF_Z_MSB_t;
308 
309 /*--------------------------------
310 ** Register: PROD_REV
311 ** Enum: FXLS896x_PROD_REV
312 ** --
313 ** Offset : 0x12 Product revision number in BCD format.
314 ** ------------------------------*/
315 typedef union
316 {
317  struct
318  {
319  uint8_t prod_rev_min : 4; /* Product revision info, minor product revision value with range 0 to 9 in */
320  /* BCD format. */
321 
322  uint8_t prod_rev_maj : 4; /* Product revision info, major product revision value with range 1 to 9 in */
323  /* BCD format. */
324 
325  } b;
326  uint8_t w;
327 } FXLS896x_PROD_REV_t;
328 
329 /*
330 ** PROD_REV - Bit field mask definitions
331 */
332 #define FXLS896x_PROD_REV_PROD_REV_MIN_MASK ((uint8_t)0x0F)
333 #define FXLS896x_PROD_REV_PROD_REV_MIN_SHIFT ((uint8_t)0)
334 
335 #define FXLS896x_PROD_REV_PROD_REV_MAJ_MASK ((uint8_t)0xF0)
336 #define FXLS896x_PROD_REV_PROD_REV_MAJ_SHIFT ((uint8_t)4)
337 
338 /*--------------------------------
339 ** Register: WHO_AM_I
340 ** Enum: FXLS896x_WHO_AM_I
341 ** --
342 ** Offset : 0x13 8-bit NXP unique sensor Product ID.
343 ** ------------------------------*/
344 typedef uint8_t FXLS896x_WHO_AM_I_t;
345 
346 /*--------------------------------
347 ** Register: SYS_MODE
348 ** Enum: FXLS896x_SYS_MODE
349 ** --
350 ** Offset : 0x14 Current System Operating Mode.
351 ** ------------------------------*/
352 typedef union
353 {
354  struct
355  {
356  uint8_t sys_mode : 2; /* Current System operating mode. */
357 
358  uint8_t buf_gate_cnt : 5; /* number of OOR periods that have elapsed since the BUF _GATE_ERR flag was asserted. */
359 
360  uint8_t buf_gate_error : 1; /* Buffer gate error flag. */
361 
362  } b;
363  uint8_t w;
364 } FXLS896x_SYS_MODE_t;
365 
366 /*
367 ** SYS_MODE - Bit field mask definitions
368 */
369 #define FXLS896x_SYS_MODE_BUF_GATE_ERROR_MASK ((uint8_t)0x03)
370 #define FXLS896x_SYS_MODE_BUF_GATE_ERROR_SHIFT ((uint8_t)0)
371 
372 #define FXLS896x_SYS_MODE_BUF_GATE_CNT_MASK ((uint8_t)0x7C)
373 #define FXLS896x_SYS_MODE_BUF_GATE_CNT_SHIFT ((uint8_t)2)
374 
375 #define FXLS896x_SYS_MODE_SYS_MODE_MASK ((uint8_t)0x80)
376 #define FXLS896x_SYS_MODE_SYS_MODE_SHIFT ((uint8_t)7)
377 
378 /*
379 ** SYS_MODE - Bit field value definitions
380 */
381 #define FXLS896x_SYS_MODE_BUF_GARE_ERROR_NO ((uint8_t)0x00) /* Not Detected. */
382 #define FXLS896x_SYS_MODE_BUF_GARE_ERROR_YES ((uint8_t)0x80)/* Detected. */
383 #define FXLS896x_SYS_MODE_SYS_MODE_STANDBY ((uint8_t)0x00) /* Standby Mode. */
384 #define FXLS896x_SYS_MODE_SYS_MODE_WAKE ((uint8_t)0x01) /* Wake Mode. */
385 #define FXLS896x_SYS_MODE_SYS_MODE_SLEEP ((uint8_t)0x02) /* Sleep Mode. */
386 #define FXLS896x_SYS_MODE_SYS_MODE_EXT_TRIG ((uint8_t)0x03) /* External Trigger Mode. */
387  /*------------------------------*/
388 
389 /*--------------------------------
390 ** Register: SENS_CONFIG1
391 ** Enum: FXLS896x_SENS_CONFIG1
392 ** --
393 ** Offset : 0x15 Configuration register 1.
394 ** ------------------------------*/
395 typedef union
396 {
397  struct
398  {
399  uint8_t active : 1; /* Standby/Active mode selection */
400 
401  uint8_t fsr : 2; /* Full-scale measurement range (FSR) selection. */
402 
403  uint8_t spi_m : 1; /* SPI interface mode selection; selects between 3- and 4-wire operating */
404  /* modes for the SPI interface. */
405 
406  uint8_t st_pol : 1; /* Self-Test Displacement Polarity */
407 
408  uint8_t st_axis_sel : 2; /* Self-Test Axis Selection */
409 
410  uint8_t rst : 1; /* The RST bit may be used to initiate a software reset. */
411 
412  } b;
413  uint8_t w;
414 } FXLS896x_SENS_CONFIG1_t;
415 
416 /*
417 ** SENS_CONFIG1 - Bit field mask definitions
418 */
419 #define FXLS896x_SENS_CONFIG1_ACTIVE_MASK ((uint8_t)0x01)
420 #define FXLS896x_SENS_CONFIG1_ACTIVE_SHIFT ((uint8_t)0)
421 
422 #define FXLS896x_SENS_CONFIG1_FSR_MASK ((uint8_t)0x06)
423 #define FXLS896x_SENS_CONFIG1_FSR_SHIFT ((uint8_t)1)
424 
425 #define FXLS896x_SENS_CONFIG1_SPI_M_MASK ((uint8_t)0x08)
426 #define FXLS896x_SENS_CONFIG1_SPI_M_SHIFT ((uint8_t)3)
427 
428 #define FXLS896x_SENS_CONFIG1_ST_POL_MASK ((uint8_t)0x10)
429 #define FXLS896x_SENS_CONFIG1_ST_POL_SHIFT ((uint8_t)4)
430 
431 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_MASK ((uint8_t)0x60)
432 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_SHIFT ((uint8_t)5)
433 
434 #define FXLS896x_SENS_CONFIG1_RST_MASK ((uint8_t)0x80)
435 #define FXLS896x_SENS_CONFIG1_RST_SHIFT ((uint8_t)7)
436 
437 /*
438 ** SENS_CONFIG1 - Bit field value definitions
439 */
440 #define FXLS896x_SENS_CONFIG1_RST_RST ((uint8_t)0x80) /* Trigger Reset */
441 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_DISABLED \
442  ((uint8_t)0x00) /* Self-Test function is disabled */
443 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_X ((uint8_t)0x20) /* Self-Test function is enabled for X-axis */
444 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_Y ((uint8_t)0x40) /* Self-Test function is enabled for Y-axis */
445 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_Z ((uint8_t)0x60) /* Self-Test function is enabled for Z-axis */
446 #define FXLS896x_SENS_CONFIG1_ST_POL_POSITIVE ((uint8_t)0x00) /* Proof mass displacement for the selected axis */
447  /* is in the positive direction. */
448 #define FXLS896x_SENS_CONFIG1_ST_POL_NEGATIVE ((uint8_t)0x10) /* Proof mass displacement for the selected axis */
449  /* is in the negative direction. */
450 #define FXLS896x_SENS_CONFIG1_SPI_M_FOUR ((uint8_t)0x00) /* 4-wire interface mode is selected. */
451 #define FXLS896x_SENS_CONFIG1_SPI_M_THREE ((uint8_t)0x08) /* 3-wire interface mode is selected. */
452 #define FXLS896x_SENS_CONFIG1_FSR_2G ((uint8_t)0x00) /* ±2g; 0.98 mg/LSB (1024 LSB/g) nominal */
453  /* sensitivity. */
454 #define FXLS896x_SENS_CONFIG1_FSR_4G ((uint8_t)0x02) /* ±4g; 1.95 mg/LSB (512 LSB/g) nominal */
455  /* sensitivity. */
456 #define FXLS896x_SENS_CONFIG1_FSR_8G ((uint8_t)0x04) /* ±8g; 3.91 mg/LSB (256 LSB/g) nominal */
457  /* sensitivity. */
458 #define FXLS896x_SENS_CONFIG1_FSR_16G ((uint8_t)0x06) /* ±16g; 7.81 mg/LSB (128 LSB/g) nominal */
459  /* sensitivity. */
460 #define FXLS896x_SENS_CONFIG1_ACTIVE_STANDBY ((uint8_t)0x00) /* Standby mode. */
461 #define FXLS896x_SENS_CONFIG1_ACTIVE_ACTIVE ((uint8_t)0x01) /* Active mode. */
462  /*------------------------------*/
463 
464 /*--------------------------------
465 ** Register: SENS_CONFIG2
466 ** Enum: FXLS896x_SENS_CONFIG2
467 ** --
468 ** Offset : 0x16 Configuration register 2.
469 ** ------------------------------*/
470 typedef union
471 {
472  struct
473  {
474  uint8_t f_read : 1; /* Fast-read mode selection. */
475 
476  uint8_t anic_temp : 1; /* Temperature output data auto-increment control. */
477 
478  uint8_t _reserved_ : 1;
479  uint8_t le_be : 1; /* Little/Big-endian output mode selection. */
480 
481  uint8_t sleep_pm : 2; /* SLEEP power mode selection. */
482 
483  uint8_t wake_pm : 2; /* WAKE power mode selection. */
484 
485  } b;
486  uint8_t w;
487 } FXLS896x_SENS_CONFIG2_t;
488 
489 /*
490 ** SENS_CONFIG2 - Bit field mask definitions
491 */
492 #define FXLS896x_SENS_CONFIG2_F_READ_MASK ((uint8_t)0x01)
493 #define FXLS896x_SENS_CONFIG2_F_READ_SHIFT ((uint8_t)0)
494 
495 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_MASK ((uint8_t)0x02)
496 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_SHIFT ((uint8_t)1)
497 
498 #define FXLS896x_SENS_CONFIG2_LE_BE_MASK ((uint8_t)0x08)
499 #define FXLS896x_SENS_CONFIG2_LE_BE_SHIFT ((uint8_t)3)
500 
501 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_MASK ((uint8_t)0x30)
502 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_SHIFT ((uint8_t)4)
503 
504 #define FXLS896x_SENS_CONFIG2_WAKE_PM_MASK ((uint8_t)0xC0)
505 #define FXLS896x_SENS_CONFIG2_WAKE_PM_SHIFT ((uint8_t)6)
506 
507 /*
508 ** SENS_CONFIG2 - Bit field value definitions
509 */
510 #define FXLS896x_SENS_CONFIG2_WAKE_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */
511 #define FXLS896x_SENS_CONFIG2_WAKE_PM_HIGH_PERF ((uint8_t)0x40) /* High Performance Mode is selected. */
512 #define FXLS896x_SENS_CONFIG2_WAKE_PM_FLEX_PERF ((uint8_t)0x80) /* Flexible Performance Mode is selected. */
513 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */
514 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_HIGH_PERF ((uint8_t)0x10) /* High Performance Mode is selected. */
515 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_FLEX_PERF ((uint8_t)0x20) /* Flexible Performance Mode is selected. */
516 #define FXLS896x_SENS_CONFIG2_LE_BE_LE ((uint8_t)0x00) /* Little-endian output mode is selected. */
517 #define FXLS896x_SENS_CONFIG2_LE_BE_BE ((uint8_t)0x08) /* Big-endian output mode is selected. */
518 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_DIS ((uint8_t)0x00) /* TEMP_OUT register content is not included in */
519  /* auto-increment address range. */
520 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_EN ((uint8_t)0x02) /* TEMP_OUT register content is included in */
521  /* auto-increment address range. */
522 #define FXLS896x_SENS_CONFIG2_F_READ_NORMAL ((uint8_t)0x00) /* Normal read mode. */
523 #define FXLS896x_SENS_CONFIG2_F_READ_FAST ((uint8_t)0x01) /* Fast read mode. */
524  /*------------------------------*/
525 
526 /*--------------------------------
527 ** Register: SENS_CONFIG3
528 ** Enum: FXLS896x_SENS_CONFIG3
529 ** --
530 ** Offset : 0x17 Configuration register 3.
531 ** ------------------------------*/
532 typedef union
533 {
534  struct
535  {
536  uint8_t sleep_odr : 4; /* Sleep ODR */
537 
538  uint8_t wake_odr : 4; /* Wake ODR */
539 
540  } b;
541  uint8_t w;
542 } FXLS896x_SENS_CONFIG3_t;
543 
544 /*
545 ** SENS_CONFIG3 - Bit field mask definitions
546 */
547 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_MASK ((uint8_t)0x0F)
548 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_SHIFT ((uint8_t)0)
549 
550 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_MASK ((uint8_t)0xF0)
551 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_SHIFT ((uint8_t)4)
552 
553 /*
554 ** SENS_CONFIG3 - Bit field value definitions
555 */
556 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_3200HZ ((uint8_t)0x00)
557 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_1600HZ ((uint8_t)0x10)
558 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_800HZ ((uint8_t)0x20)
559 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_400HZ ((uint8_t)0x30)
560 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_200HZ ((uint8_t)0x40)
561 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_100HZ ((uint8_t)0x50)
562 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_50HZ ((uint8_t)0x60)
563 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_25HZ ((uint8_t)0x70)
564 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_12_5HZ ((uint8_t)0x80)
565 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_6_25HZ ((uint8_t)0x90) /* 6.25 HZ */
566 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_3_125HZ ((uint8_t)0xa0) /* 3.125 HZ */
567 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_1_563HZ ((uint8_t)0xb0) /* 1.563 HZ */
568 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_0_781HZ ((uint8_t)0xc0) /* 0.781 HZ */
569 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_3200HZ ((uint8_t)0x00)
570 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_1600HZ ((uint8_t)0x01)
571 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_800HZ ((uint8_t)0x02)
572 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_400HZ ((uint8_t)0x03)
573 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_200HZ ((uint8_t)0x04)
574 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_100HZ ((uint8_t)0x05)
575 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_50HZ ((uint8_t)0x06)
576 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_25HZ ((uint8_t)0x07)
577 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_12_5HZ ((uint8_t)0x08)
578 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_6_25HZ ((uint8_t)0x09) /* 6.25 HZ */
579 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_3_125HZ ((uint8_t)0x0a) /* 3.125 HZ */
580 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_1_563HZ ((uint8_t)0x0b) /* 1.563 HZ */
581 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_0_781HZ ((uint8_t)0x0c) /* 0.781 HZ */
582  /*------------------------------*/
583 
584 /*--------------------------------
585 ** Register: SENS_CONFIG4
586 ** Enum: FXLS896x_SENS_CONFIG4
587 ** --
588 ** Offset : 0x18 Configuration register 4.
589 ** ------------------------------*/
590 typedef union
591 {
592  struct
593  {
594  uint8_t int_pol : 1; /* Interrupt logic polarity on INT1 and INT2 pins. */
595 
596  uint8_t int_pp_od : 1; /* INT1 and INT2 pins output driver selection. */
597 
598  uint8_t int2_func : 1; /* INT2 output / EXT_TRIG input pin selection. */
599 
600  uint8_t drdy_pul : 1; /* Pulse generation option for DRDY event. */
601 
602  uint8_t wk_orient : 1; /* Orientation change event Auto-WAKE/SLEEP transition source enable. */
603 
604  uint8_t wk_sdcd_ot : 1; /* SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable. */
605 
606  uint8_t wk_sdcd_wt : 1; /* SDCD within thresholds event Auto-WAKE/SLEEP transition source enable. */
607 
608  uint8_t ext_trig_m : 1; /* External trigger function acquisition mode. */
609 
610  } b;
611  uint8_t w;
612 } FXLS896x_SENS_CONFIG4_t;
613 
614 /*
615 ** SENS_CONFIG4 - Bit field mask definitions
616 */
617 #define FXLS896x_SENS_CONFIG4_INT_POL_MASK ((uint8_t)0x01)
618 #define FXLS896x_SENS_CONFIG4_INT_POL_SHIFT ((uint8_t)0)
619 
620 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_MASK ((uint8_t)0x02)
621 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_SHIFT ((uint8_t)1)
622 
623 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_MASK ((uint8_t)0x04)
624 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_SHIFT ((uint8_t)2)
625 
626 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_MASK ((uint8_t)0x08)
627 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_SHIFT ((uint8_t)3)
628 
629 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_MASK ((uint8_t)0x10)
630 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_SHIFT ((uint8_t)4)
631 
632 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_MASK ((uint8_t)0x20)
633 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_SHIFT ((uint8_t)5)
634 
635 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_MASK ((uint8_t)0x40)
636 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_SHIFT ((uint8_t)6)
637 
638 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_MASK ((uint8_t)0x80)
639 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_SHIFT ((uint8_t)7)
640 
641 /*
642 ** SENS_CONFIG4 - Bit field value definitions
643 */
644 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_SINGLE ((uint8_t)0x00) /* Each positive going trigger edge causes a */
645  /* single ADC acquisition to be made. */
646 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_MULTIPLE ((uint8_t)0x80) /* Each positive going trigger edge causes the */
647 /* number of acquisitions. */
648 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_DIS ((uint8_t)0x00) /* SDCD within thresholds event is not used to */
649  /* prevent entry into/trigger. */
650 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_EN ((uint8_t)0x40) /* SDCD within thresholds event is used to prevent */
651  /* entry into/trigger an exit from SLEEP mode. */
652 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_DIS ((uint8_t)0x00) /* SDCD outside thresholds event is not used to */
653  /* prevent entry into/trigger. */
654 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_EN ((uint8_t)0x20) /* SDCD outside thresholds event is used to */
655  /* prevent entry into/trigger an exit from SLEEP */
656  /* mode. */
657 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_DIS ((uint8_t)0x00) /* Orientation change condition is not used as an */
658  /* event to prevent entry into /trigger an exit */
659  /* from SLEEP mode. */
660 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_EN ((uint8_t)0x10) /* Orientation change condition is used as an */
661  /* event to prevent entry into/trigger an exit */
662  /* from SLEEP mode. */
663 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_DIS ((uint8_t)0x00) /* A SRC_DRDY event is output on the INTx pin as */
664  /* an active high or active low signal. */
665 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_EN ((uint8_t)0x08) /* A 32 μs (nominal) duration pulse is output on */
666  /* the configured INTx pin once per ODR cycle. */
667 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_INT2 ((uint8_t)0x00) /* INT2/EXT_TRIG pin is configured for the INT2 */
668  /* output function. */
669 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_EXT_TRIG \
670  ((uint8_t)0x04) /* INT2/EXT_TRIG pin is configured as the EXT_TRIG \ \ \
671  */
672 /* input function. */
673 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_PUSH_PULL ((uint8_t)0x00) /* INTx output pin driver is push-pull type. */
674 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_OPEN_DRAIN \
675  ((uint8_t)0x02) /* INTx output pin driver is */
676  /* open-drain/open-source type. */
677 #define FXLS896x_SENS_CONFIG4_INT_POL_ACT_LOW ((uint8_t)0x00) /* Active low:Interrupt events are signaled with a */
678  /* logical 0 level. */
679 #define FXLS896x_SENS_CONFIG4_INT_POL_ACT_HIGH ((uint8_t)0x01) /* Active high: interrupt events are signaled with */
680  /* a logical 1 level. */
681  /*------------------------------*/
682 
683 /*--------------------------------
684 ** Register: SENS_CONFIG5
685 ** Enum: FXLS896x_SENS_CONFIG5
686 ** --
687 ** Offset : 0x19 Configuration register 5.
688 ** ------------------------------*/
689 typedef union
690 {
691  struct
692  {
693  uint8_t hibernate_en : 1; /* Hibernate mode enable. */
694 
695  uint8_t z_dis : 1; /* Z-axis auto-increment disable. */
696 
697  uint8_t y_dis : 1; /* Y-axis auto-increment disable. */
698 
699  uint8_t x_dis : 1; /* X-axis auto-increment disable. */
700 
701  uint8_t vecm_en : 1; /* Vector Magnitude calculation enable. */
702 
703  } b;
704  uint8_t w;
705 } FXLS896x_SENS_CONFIG5_t;
706 
707 /*
708 ** SENS_CONFIG5 - Bit field mask definitions
709 */
710 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_MASK ((uint8_t)0x01)
711 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_SHIFT ((uint8_t)0)
712 
713 #define FXLS896x_SENS_CONFIG5_Z_DIS_MASK ((uint8_t)0x02)
714 #define FXLS896x_SENS_CONFIG5_Z_DIS_SHIFT ((uint8_t)1)
715 
716 #define FXLS896x_SENS_CONFIG5_Y_DIS_MASK ((uint8_t)0x04)
717 #define FXLS896x_SENS_CONFIG5_Y_DIS_SHIFT ((uint8_t)2)
718 
719 #define FXLS896x_SENS_CONFIG5_X_DIS_MASK ((uint8_t)0x08)
720 #define FXLS896x_SENS_CONFIG5_X_DIS_SHIFT ((uint8_t)3)
721 
722 #define FXLS896x_SENS_CONFIG5_VECM_EN_MASK ((uint8_t)0x10)
723 #define FXLS896x_SENS_CONFIG5_VECM_EN_SHIFT ((uint8_t)4)
724 
725 /*
726 ** SENS_CONFIG5 - Bit field value definitions
727 */
728 #define FXLS896x_SENS_CONFIG5_VECM_EN_DIS ((uint8_t)0x00) /* 12-bit vector magnitude result is not */
729  /* calculated on every ODR cycle. */
730 #define FXLS896x_SENS_CONFIG5_VECM_EN_EN ((uint8_t)0x10) /* 12-bit vector magnitude result is calculated on */
731  /* every ODR cycle. */
732 #define FXLS896x_SENS_CONFIG5_X_DIS_EN ((uint8_t)0x00) /* X-axis measurement is included in the */
733  /* auto-increment address range. */
734 #define FXLS896x_SENS_CONFIG5_X_DIS_DIS ((uint8_t)0x08) /* X-axis measurement is excluded from the */
735  /* auto-increment address range. */
736 #define FXLS896x_SENS_CONFIG5_Y_DIS_EN ((uint8_t)0x00) /* Y-axis measurement is included in the */
737  /* auto-increment address range. */
738 #define FXLS896x_SENS_CONFIG5_Y_DIS_DIS ((uint8_t)0x04) /* Y-axis measurement is excluded from the */
739  /* auto-increment address range. */
740 #define FXLS896x_SENS_CONFIG5_Z_DIS_EN ((uint8_t)0x00) /* Z-axis measurement is included in the */
741  /* auto-increment address range. */
742 #define FXLS896x_SENS_CONFIG5_Z_DIS_DIS ((uint8_t)0x02) /* Z-axis measurement is excluded from the */
743  /* auto-increment address range. */
744 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_DIS ((uint8_t)0x00) /* Hibernate mode not enabled. */
745 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_EN ((uint8_t)0x01) /* Commands device to enter Hibernate mode. */
746  /*------------------------------*/
747 
748 /*--------------------------------
749 ** Register: WAKE_IDLE_LSB
750 ** Enum: FXLS896x_WAKE_IDLE_LSB
751 ** --
752 ** Offset : 0x1A LSB of 12-bit user programmable wake mode idle.
753 ** ------------------------------*/
754 typedef uint8_t FXLS896x_WAKE_IDLE_LSB_t;
755 
756 /*--------------------------------
757 ** Register: WAKE_IDLE_MSB
758 ** Enum: FXLS896x_WAKE_IDLE_MSB
759 ** --
760 ** Offset : 0x1B MSB of 12-bit user programmable wake mode idle.
761 ** ------------------------------*/
762 typedef uint8_t FXLS896x_WAKE_IDLE_MSB_t;
763 
764 /*--------------------------------
765 ** Register: SLEEP_IDLE_LSB
766 ** Enum: FXLS896x_SLEEP_IDLE_LSB
767 ** --
768 ** Offset : 0x1C LSB of 12-bit user programmable sleep mode idle.
769 ** ------------------------------*/
770 typedef uint8_t FXLS896x_SLEEP_IDLE_LSB_t;
771 
772 /*--------------------------------
773 ** Register: SLEEP_IDLE_MSB
774 ** Enum: FXLS896x_SLEEP_IDLE_MSB
775 ** --
776 ** Offset : 0x1D MSB of 12-bit user programmable sleep mode idle.
777 ** ------------------------------*/
778 typedef uint8_t FXLS896x_SLEEP_IDLE_MSB_t;
779 
780 /*--------------------------------
781 ** Register: ASLP_COUNT_LSB
782 ** Enum: FXLS896x_ASLP_COUNT_LSB
783 ** --
784 ** Offset : 0x1E LSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode.
785 ** ------------------------------*/
786 typedef uint8_t FXLS896x_ASLP_COUNT_LSB_t;
787 
788 /*--------------------------------
789 ** Register: ASLP_COUNT_MSB
790 ** Enum: FXLS896x_ASLP_COUNT_MSB
791 ** --
792 ** Offset : 0x1F MSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode.
793 ** ------------------------------*/
794 typedef uint8_t FXLS896x_ASLP_COUNT_MSB_t;
795 
796 /*--------------------------------
797 ** Register: INT_EN
798 ** Enum: FXLS896x_INT_EN
799 ** --
800 ** Offset : 0x20 Interrupt output enable register.
801 ** ------------------------------*/
802 typedef union
803 {
804  struct
805  {
806  uint8_t wake_out_en : 1; /* WAKE power state output enable. */
807 
808  uint8_t boot_dis : 1; /* Boot interrupt output disable. */
809 
810  uint8_t aslp_en : 1; /* Auto-WAKE/SLEEP interrupt output enable. */
811 
812  uint8_t orient_en : 1; /* Orientation interrupt output enable. */
813 
814  uint8_t sdcd_wt_en : 1; /* SDCD within thresholds interrupt output enable. */
815 
816  uint8_t sdcd_ot_en : 1; /* SDCD outside of thresholds interrupt output enable. */
817 
818  uint8_t buf_en : 1; /* Output data buffer interrupt output enable */
819  uint8_t drdy_en : 1; /* Data Ready interrupt output enable. */
820 
821  } b;
822  uint8_t w;
823 } FXLS896x_INT_EN_t;
824 
825 /*
826 ** INT_EN - Bit field mask definitions
827 */
828 #define FXLS896x_INT_EN_WAKE_OUT_EN_MASK ((uint8_t)0x01)
829 #define FXLS896x_INT_EN_WAKE_OUT_EN_SHIFT ((uint8_t)0)
830 
831 #define FXLS896x_INT_EN_BOOT_DIS_MASK ((uint8_t)0x02)
832 #define FXLS896x_INT_EN_BOOT_DIS_SHIFT ((uint8_t)1)
833 
834 #define FXLS896x_INT_EN_ASLP_EN_MASK ((uint8_t)0x04)
835 #define FXLS896x_INT_EN_ASLP_EN_SHIFT ((uint8_t)2)
836 
837 #define FXLS896x_INT_EN_ORIENT_EN_MASK ((uint8_t)0x08)
838 #define FXLS896x_INT_EN_ORIENT_EN_SHIFT ((uint8_t)3)
839 
840 #define FXLS896x_INT_EN_SDCD_WT_EN_MASK ((uint8_t)0x10)
841 #define FXLS896x_INT_EN_SDCD_WT_EN_SHIFT ((uint8_t)4)
842 
843 #define FXLS896x_INT_EN_SDCD_OT_EN_MASK ((uint8_t)0x20)
844 #define FXLS896x_INT_EN_SDCD_OT_EN_SHIFT ((uint8_t)5)
845 
846 #define FXLS896x_INT_EN_BUF_EN_MASK ((uint8_t)0x40)
847 #define FXLS896x_INT_EN_BUF_EN_SHIFT ((uint8_t)6)
848 
849 #define FXLS896x_INT_EN_DRDY_EN_MASK ((uint8_t)0x80)
850 #define FXLS896x_INT_EN_DRDY_EN_SHIFT ((uint8_t)7)
851 
852 /*
853 ** INT_EN - Bit field value definitions
854 */
855 #define FXLS896x_INT_EN_DRDY_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
856 #define FXLS896x_INT_EN_DRDY_EN_EN ((uint8_t)0x80) /* Interrupt enabled. */
857 #define FXLS896x_INT_EN_BUF_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
858 #define FXLS896x_INT_EN_BUF_EN_EN ((uint8_t)0x40) /* Interrupt enabled. */
859 #define FXLS896x_INT_EN_SDCD_OT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
860 #define FXLS896x_INT_EN_SDCD_OT_EN_EN ((uint8_t)0x20) /* Interrupt is routed to either the INT1 or INT2. */
861 #define FXLS896x_INT_EN_SDCD_WT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
862 #define FXLS896x_INT_EN_SDCD_WT_EN_EN ((uint8_t)0x10) /* Interrupt is routed to either the INT1 or INT2. */
863 #define FXLS896x_INT_EN_ORIENT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
864 #define FXLS896x_INT_EN_ORIENT_EN_EN ((uint8_t)0x08) /* Interrupt is enabled and signaled on either the INT1 */
865  /* or INT2. */
866 #define FXLS896x_INT_EN_ASLP_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
867 #define FXLS896x_INT_EN_ASLP_EN_EN ((uint8_t)0x04) /* Interrupt is enabled and signaled on either the INT1 */
868  /* or INT2. */
869 #define FXLS896x_INT_EN_BOOT_DIS_EN ((uint8_t)0x00) /* Boot interrupt is enabled and routed to either the */
870  /* INT1 or INT2. */
871 #define FXLS896x_INT_EN_BOOT_DIS_DIS ((uint8_t)0x02) /* Interrupt is disabled and not routed to the INTx */
872  /* output pins. */
873 #define FXLS896x_INT_EN_WAKE_OUT_EN_DIS ((uint8_t)0x00) /* The device does not signal the WAKE operating mode on */
874  /* the INTx output pin. */
875 #define FXLS896x_INT_EN_WAKE_OUT_EN_EN ((uint8_t)0x01) /* The device signals that it is currently in WAKE mode */
876  /* via the INT1 or INT2 pin. */
877  /*------------------------------*/
878 
879 /*--------------------------------
880 ** Register: INT_PIN_SEL
881 ** Enum: FXLS896x_INT_PIN_SEL
882 ** --
883 ** Offset : 0x21 Interrupt output pin routing register, INT1 or INT2.
884 ** ------------------------------*/
885 typedef union
886 {
887  struct
888  {
889  uint8_t wk_out_int2 : 1; /* WAKE power state interrupt routing. */
890 
891  uint8_t boot_int2 : 1; /* BOOT event interrupt routing. */
892 
893  uint8_t aslp_int2 : 1; /* Auto-WAKE/SLEEP event interrupt routing. */
894 
895  uint8_t orient_int2 : 1; /* ORIENT event interrupt routing. */
896 
897  uint8_t sdcd_wt_int2 : 1; /* SDCD within thresholds event interrupt routing. */
898 
899  uint8_t sdcd_ot_int2 : 1; /* SDCD outside of thresholds event interrupt routing. */
900 
901  uint8_t buf_int2 : 1; /* Output buffer interrupt routing. */
902 
903  uint8_t drdy_int2 : 1; /* Data Ready interrupt routing. */
904 
905  } b;
906  uint8_t w;
907 } FXLS896x_INT_PIN_SEL_t;
908 
909 /*
910 ** INT_PIN_SEL - Bit field mask definitions
911 */
912 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_MASK ((uint8_t)0x01)
913 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_SHIFT ((uint8_t)0)
914 
915 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_MASK ((uint8_t)0x02)
916 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_SHIFT ((uint8_t)1)
917 
918 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_MASK ((uint8_t)0x04)
919 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_SHIFT ((uint8_t)2)
920 
921 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_MASK ((uint8_t)0x08)
922 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_SHIFT ((uint8_t)3)
923 
924 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_MASK ((uint8_t)0x10)
925 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_SHIFT ((uint8_t)4)
926 
927 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_MASK ((uint8_t)0x20)
928 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_SHIFT ((uint8_t)5)
929 
930 #define FXLS896x_INT_PIN_SEL_BUF_INT2_MASK ((uint8_t)0x40)
931 #define FXLS896x_INT_PIN_SEL_BUF_INT2_SHIFT ((uint8_t)6)
932 
933 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_MASK ((uint8_t)0x80)
934 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_SHIFT ((uint8_t)7)
935 
936 /*
937 ** INT_PIN_SEL - Bit field value definitions
938 */
939 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
940  /* enabled. */
941 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_EN ((uint8_t)0x80) /* Interrupt signal is routed to INT2 pin if it is */
942  /* enabled. */
943 #define FXLS896x_INT_PIN_SEL_BUF_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
944  /* enabled. */
945 #define FXLS896x_INT_PIN_SEL_BUF_INT2_EN ((uint8_t)0x40) /* Interrupt signal is routed to INT2 pin if it is */
946  /* enabled. */
947 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
948  /* enabled. */
949 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_EN ((uint8_t)0x20) /* Interrupt signal is routed to INT2 pin if it is */
950  /* enabled. */
951 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
952  /* enabled. */
953 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_EN ((uint8_t)0x10) /* Interrupt signal is routed to INT2 pin if it is */
954  /* enabled. */
955 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
956  /* enabled. */
957 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_EN ((uint8_t)0x08) /* Interrupt signal is routed to INT2 pin if it is */
958  /* enabled. */
959 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
960  /* enabled. */
961 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_EN ((uint8_t)0x04) /* Interrupt signal is routed to INT2 pin if it is */
962  /* enabled. */
963 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
964  /* enabled. */
965 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_EN ((uint8_t)0x02) /* Interrupt signal is routed to INT2 pin if it is */
966  /* enabled. */
967 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
968  /* enabled. */
969 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_EN ((uint8_t)0x01) /* Interrupt signal is routed to INT2 pin if it is */
970  /* enabled. */
971  /*------------------------------*/
972 
973 /*--------------------------------
974 ** Register: OFF_X
975 ** Enum: FXLS896x_OFF_X
976 ** --
977 ** Offset : 0x22 X-Acceleration zero-g offset.
978 ** ------------------------------*/
979 typedef uint8_t FXLS896x_OFF_X_t;
980 
981 /*--------------------------------
982 ** Register: OFF_Y
983 ** Enum: FXLS896x_OFF_Y
984 ** --
985 ** Offset : 0x23 Y-Acceleration zero-g offset.
986 ** ------------------------------*/
987 typedef uint8_t FXLS896x_OFF_Y_t;
988 
989 /*--------------------------------
990 ** Register: OFF_Z
991 ** Enum: FXLS896x_OFF_Z
992 ** --
993 ** Offset : 0x24 Z-Acceleration zero-g offset.
994 ** ------------------------------*/
995 typedef uint8_t FXLS896x_OFF_Z_t;
996 
997 
998 
999 /*--------------------------------
1000 ** Register: BUF_CONFIG1
1001 ** Enum: FXLS896x_BUF_CONFIG1
1002 ** --
1003 ** Offset : 0x26 Buf configuration1.
1004 ** ------------------------------*/
1005 typedef union {
1006  struct {
1007  uint8_t trg_orient : 1; /* Orientation change event trigger enable */
1008 
1009  uint8_t _reserved_ : 1;
1010  uint8_t trg_sdcd_ot : 1; /* SDCD outside-of-thresholds event buffer trigger enable */
1011 
1012  uint8_t trg_sdcd_wt : 1; /* SDCD within-thresholds event trigger enable */
1013 
1014  uint8_t buf_gate : 1; /* Output data buffer gate enable */
1015 
1016  uint8_t buf_mode : 2; /* Buffer data collection mode */
1017 
1018  uint8_t buf_type : 1; /* Buffer data read out order */
1019 
1020  } b;
1021  uint8_t w;
1022 } FXLS896x_BUF_CONFIG1_t;
1023 
1024 
1025 /*
1026 ** BUF_CONFIG1 - Bit field mask definitions
1027 */
1028 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_MASK ((uint8_t) 0x01)
1029 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_SHIFT ((uint8_t) 0)
1030 
1031 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_MASK ((uint8_t) 0x04)
1032 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_SHIFT ((uint8_t) 2)
1033 
1034 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_MASK ((uint8_t) 0x08)
1035 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_SHIFT ((uint8_t) 3)
1036 
1037 #define FXLS896x_BUF_CONFIG1_BUF_GATE_MASK ((uint8_t) 0x10)
1038 #define FXLS896x_BUF_CONFIG1_BUF_GATE_SHIFT ((uint8_t) 4)
1039 
1040 #define FXLS896x_BUF_CONFIG1_BUF_MODE_MASK ((uint8_t) 0x60)
1041 #define FXLS896x_BUF_CONFIG1_BUF_MODE_SHIFT ((uint8_t) 5)
1042 
1043 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_MASK ((uint8_t) 0x80)
1044 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_SHIFT ((uint8_t) 7)
1045 
1046 
1047 /*
1048 ** BUF_CONFIG1 - Bit field value definitions
1049 */
1050 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_FIFO ((uint8_t) 0x00) /* In FIFO mode */
1051 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_FILO ((uint8_t) 0x80) /* First In Last Out (FILO) */
1052 #define FXLS896x_BUF_CONFIG1_BUF_MODE_DIS ((uint8_t) 0x00) /* Buffer is disabled */
1053 #define FXLS896x_BUF_CONFIG1_BUF_MODE_STREAM_MODE ((uint8_t) 0x20) /* Stream Mode */
1054 #define FXLS896x_BUF_CONFIG1_BUF_MODE_STOP_MODE ((uint8_t) 0x40) /* Stop mode */
1055 #define FXLS896x_BUF_CONFIG1_BUF_MODE_TRIGGER_MODE ((uint8_t) 0x60) /* Trigger Mode */
1056 #define FXLS896x_BUF_CONFIG1_BUF_GATE_BY_PASSED ((uint8_t) 0x00) /* Buffer gate is bypassed. */
1057 #define FXLS896x_BUF_CONFIG1_BUF_GATE_ENABLED ((uint8_t) 0x10) /* The Buffer gate input is enabled. */
1058 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1059 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_EN ((uint8_t) 0x08) /* Trigger source is enabled. */
1060 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1061 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_EN ((uint8_t) 0x04) /* Trigger source is enabled. */
1062 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1063 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_EN ((uint8_t) 0x01) /* Trigger source is enabled. */
1064 /*------------------------------*/
1065 
1066 
1067 
1068 /*--------------------------------
1069 ** Register: BUF_CONFIG2
1070 ** Enum: FXLS896x_BUF_CONFIG2
1071 ** --
1072 ** Offset : 0x27 buf configuration2.
1073 ** ------------------------------*/
1074 typedef union {
1075  struct {
1076  uint8_t buf_wmrk : 6; /* Buffer sample count watermark */
1077 
1078  uint8_t wake_src_buf : 1; /* Buffer WAKE-to-SLEEP transition source enable */
1079 
1080  uint8_t buf_flush : 1; /* Buffer flush enable */
1081 
1082  } b;
1083  uint8_t w;
1084 } FXLS896x_BUF_CONFIG2_t;
1085 
1086 
1087 /*
1088 ** BUF_CONFIG2 - Bit field mask definitions
1089 */
1090 #define FXLS896x_BUF_CONFIG2_BUF_WMRK_MASK ((uint8_t) 0x3F)
1091 #define FXLS896x_BUF_CONFIG2_BUF_WMRK_SHIFT ((uint8_t) 0)
1092 
1093 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_MASK ((uint8_t) 0x40)
1094 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_SHIFT ((uint8_t) 6)
1095 
1096 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_MASK ((uint8_t) 0x80)
1097 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_SHIFT ((uint8_t) 7)
1098 
1099 
1100 /*
1101 ** BUF_CONFIG2 - Bit field value definitions
1102 */
1103 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_COMPLETED ((uint8_t) 0x00) /* Buffer flush operation not pending/completed. */
1104 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_EN ((uint8_t) 0x80) /* Buffer flush enable. */
1105 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_IGNORED ((uint8_t) 0x00) /* BUF_WMRK and BUF_OVF and event flags are ignored */
1106  /* by the auto-WAKE/SLEEP function. */
1107 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_EN ((uint8_t) 0x40) /* BUF_WMRK and BUF_OVF event flags are used by the */
1108  /* auto-WAKE/SLEEP function */
1109 
1110 
1111 /*--------------------------------
1112 ** Register: ORIENT_STATUS
1113 ** Enum: FXLS896x_ORIENT_STATUS
1114 ** --
1115 ** Offset : 0x28 Orientation event status.
1116 ** ------------------------------*/
1117 typedef union
1118 {
1119  struct
1120  {
1121  uint8_t bafro : 1; /* Back or front orientation. */
1122 
1123  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
1124 
1125  uint8_t _reserved_ : 3;
1126  uint8_t lo : 1; /* Z-tilt angle lockout. */
1127 
1128  uint8_t new_orient : 1; /* Orientation status change flag. */
1129 
1130  } b;
1131  uint8_t w;
1132 } FXLS896x_ORIENT_STATUS_t;
1133 
1134 /*
1135 ** ORIENT_STATUS - Bit field mask definitions
1136 */
1137 #define FXLS896x_ORIENT_STATUS_BAFRO_MASK ((uint8_t)0x01)
1138 #define FXLS896x_ORIENT_STATUS_BAFRO_SHIFT ((uint8_t)0)
1139 
1140 #define FXLS896x_ORIENT_STATUS_LAPO_MASK ((uint8_t)0x06)
1141 #define FXLS896x_ORIENT_STATUS_LAPO_SHIFT ((uint8_t)1)
1142 
1143 #define FXLS896x_ORIENT_STATUS_LO_MASK ((uint8_t)0x40)
1144 #define FXLS896x_ORIENT_STATUS_LO_SHIFT ((uint8_t)6)
1145 
1146 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_MASK ((uint8_t)0x80)
1147 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_SHIFT ((uint8_t)7)
1148 
1149 /*
1150 ** ORIENT_STATUS - Bit field value definitions
1151 */
1152 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_NO_CHANGE \
1153  ((uint8_t)0x00) /* No change in orientation detected. */
1154 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_CHANGED ((uint8_t)0x80) /* BAFRO and/or LAPO and/or Z-tilt lockout value */
1155 /* has changed. */
1156 #define FXLS896x_ORIENT_STATUS_LO_NOT_DETECTED ((uint8_t)0x00) /* Lockout condition has not been detected. */
1157 #define FXLS896x_ORIENT_STATUS_LO_DETECTED ((uint8_t)0x40) /* Z-tilt lockout trip angle has been exceeded. */
1158  /* Lockout condition has been detected. */
1159 #define FXLS896x_ORIENT_STATUS_LAPO_UP ((uint8_t)0x00) /* Portrait up. */
1160 #define FXLS896x_ORIENT_STATUS_LAPO_DOWN ((uint8_t)0x02) /* Portrait down. */
1161 #define FXLS896x_ORIENT_STATUS_LAPO_RIGHT ((uint8_t)0x04) /* Landscape right. */
1162 #define FXLS896x_ORIENT_STATUS_LAPO_LEFT ((uint8_t)0x06) /* Landscape left. */
1163 #define FXLS896x_ORIENT_STATUS_BAFRO_FRONT ((uint8_t)0x00) /* The device is in the front-facing orientation. */
1164 #define FXLS896x_ORIENT_STATUS_BAFRO_BACK ((uint8_t)0x01) /* The device is in the back-facing orientation. */
1165  /*------------------------------*/
1166 
1167 /*--------------------------------
1168 ** Register: ORIENT_CONFIG
1169 ** Enum: FXLS896x_ORIENT_CONFIG
1170 ** --
1171 ** Offset : 0x29 Orientation detection function configuration.
1172 ** ------------------------------*/
1173 typedef union
1174 {
1175  struct
1176  {
1177  uint8_t _reserved_ : 6;
1178  uint8_t orient_enable : 1; /* Orientation detection function enable. */
1179 
1180  uint8_t orient_dbcntm : 1; /* Orientation debounce counter mode selection. */
1181 
1182  } b;
1183  uint8_t w;
1184 } FXLS896x_ORIENT_CONFIG_t;
1185 
1186 /*
1187 ** ORIENT_CONFIG - Bit field mask definitions
1188 */
1189 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_MASK ((uint8_t)0x40)
1190 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_SHIFT ((uint8_t)6)
1191 
1192 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_MASK ((uint8_t)0x80)
1193 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_SHIFT ((uint8_t)7)
1194 
1195 /*
1196 ** ORIENT_CONFIG - Bit field value definitions
1197 */
1198 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_DEC ((uint8_t)0x00) /* Orientation debounce counter is decremented */
1199  /* whenever the current orientation is different */
1200  /* thanthe previous one. */
1201 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_CLR ((uint8_t)0x80) /* Orientation debounce counter is cleared */
1202  /* whenever the current orientation is different */
1203  /* than the previous one. */
1204 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_DIS ((uint8_t)0x00) /* Orientation detection function is disabled. */
1205 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_EN ((uint8_t)0x40) /* Orientation detection function is enabled. */
1206  /*------------------------------*/
1207 
1208 /*--------------------------------
1209 ** Register: ORIENT_DBCOUNT
1210 ** Enum: FXLS896x_ORIENT_DBCOUNT
1211 ** --
1212 ** Offset : 0x2A Orientation detection debounce counter.
1213 ** ------------------------------*/
1214 typedef uint8_t FXLS896x_ORIENT_DBCOUNT_t;
1215 
1216 /*--------------------------------
1217 ** Register: ORIENT_BF_ZCOMP
1218 ** Enum: FXLS896x_ORIENT_BF_ZCOMP
1219 ** --
1220 ** Offset : 0x2B Orientation back/front and Z-tilt angle compensation register.
1221 ** ------------------------------*/
1222 typedef union
1223 {
1224  struct
1225  {
1226  uint8_t orient_zlock : 3; /* Z-lock out angle threshold. */
1227 
1228  uint8_t _reserved_ : 3;
1229  uint8_t orient_bkfr : 2; /* Back-Up / Front-Up trip angle threshold. */
1230 
1231  } b;
1232  uint8_t w;
1233 } FXLS896x_ORIENT_BF_ZCOMP_t;
1234 
1235 /*
1236 ** ORIENT_BF_ZCOMP - Bit field mask definitions
1237 */
1238 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_MASK ((uint8_t)0x07)
1239 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_SHIFT ((uint8_t)0)
1240 
1241 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_MASK ((uint8_t)0xC0)
1242 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_SHIFT ((uint8_t)6)
1243 
1244 /*
1245 ** ORIENT_BF_ZCOMP - Bit field value definitions
1246 */
1247 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_80_280_FB_100_260 \
1248  ((uint8_t)0x00) /* Back to front Z < 80° or Z > 280° */
1249  /* and Front to back Z > 100° and Z */
1250  /* < 260° */
1251 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_75_285_FB_105_255 \
1252  ((uint8_t)0x40) /* Back to front Z < 75° or Z > 285° */
1253  /* and Front to back Z > 105° and Z */
1254  /* < 255° */
1255 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_70_290_FB_110_250 \
1256  ((uint8_t)0x80) /* Back to front Z < 70° or Z > 290° */
1257  /* and Front to back Z > 110° and Z */
1258  /* < 250° */
1259 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_65_295_FB_115_245 \
1260  ((uint8_t)0xc0) /* Back to front Z < 65° or Z > 295° */
1261  /* and Front to back Z > 115° and Z */
1262  /* < 250° */
1263 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_13_6 ((uint8_t)0x00) /* Resultant angle 13.6 */
1264 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_17_1 ((uint8_t)0x01) /* Resultant angle 17.1 */
1265 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_20_7 ((uint8_t)0x02) /* Resultant angle 20.7 */
1266 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_24_4 ((uint8_t)0x03) /* Resultant angle 24.4 */
1267 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_28_1 ((uint8_t)0x04) /* Resultant angle 28.1 */
1268 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_32_0 ((uint8_t)0x05) /* Resultant angle 32.0 */
1269 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_36_1 ((uint8_t)0x06) /* Resultant angle 36.1 */
1270 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_40_4 ((uint8_t)0x07) /* Resultant angle 40.4 */
1271  /*------------------------------*/
1272 
1273 /*--------------------------------
1274 ** Register: ORIENT_THS_REG
1275 ** Enum: FXLS896x_ORIENT_THS_REG
1276 ** --
1277 ** Offset : 0x2C Orientation detection state change threshold angle (Portrait/Landscape) and hysteresis settings.
1278 ** ------------------------------*/
1279 typedef union
1280 {
1281  struct
1282  {
1283  uint8_t hys : 3; /* ORIENT_HYS[2:0] */
1284 
1285  uint8_t orient_ths : 5; /* ORIENT_THS[4:0] value */
1286 
1287  } b;
1288  uint8_t w;
1289 } FXLS896x_ORIENT_THS_REG_t;
1290 
1291 /*
1292 ** ORIENT_THS_REG - Bit field mask definitions
1293 */
1294 #define FXLS896x_ORIENT_THS_REG_HYS_MASK ((uint8_t)0x07)
1295 #define FXLS896x_ORIENT_THS_REG_HYS_SHIFT ((uint8_t)0)
1296 
1297 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_MASK ((uint8_t)0xF8)
1298 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_SHIFT ((uint8_t)3)
1299 
1300 /*
1301 ** ORIENT_THS_REG - Bit field value definitions
1302 */
1303 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_0_0 ((uint8_t)0x00) /* 0.0° */
1304 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_1_8 ((uint8_t)0x08) /* 1.8° */
1305 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_3_8 ((uint8_t)0x10) /* 3.8° */
1306 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_5_9 ((uint8_t)0x18) /* 5.9° */
1307 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_8_1 ((uint8_t)0x20) /* 8.1° */
1308 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_10_5 ((uint8_t)0x28) /* 10.5° */
1309 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_13_0 ((uint8_t)0x30) /* 13.0° */
1310 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_15_6 ((uint8_t)0x38) /* 15.6° */
1311 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_18_4 ((uint8_t)0x40) /* 18.4° */
1312 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_21_4 ((uint8_t)0x48) /* 21.4° */
1313 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_24_4 ((uint8_t)0x50) /* 24.4° */
1314 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_27_6 ((uint8_t)0x58) /* 27.6° */
1315 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_31_0 ((uint8_t)0x60) /* 31.0° */
1316 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_34_4 ((uint8_t)0x68) /* 34.4° */
1317 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_37_9 ((uint8_t)0x70) /* 37.9° */
1318 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_41_4 ((uint8_t)0x78) /* 41.4° */
1319 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_45_0 ((uint8_t)0x80) /* 45.0° */
1320 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_48_6 ((uint8_t)0x88) /* 48.6° */
1321 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_52_1 ((uint8_t)0x90) /* 52.1° */
1322 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_55_6 ((uint8_t)0x98) /* 55.6° */
1323 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_59_0 ((uint8_t)0xa0) /* 59.0° */
1324 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_62_4 ((uint8_t)0xa8) /* 62.4° */
1325 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_65_6 ((uint8_t)0xb0) /* 65.6° */
1326 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_68_6 ((uint8_t)0xb8) /* 68.6° */
1327 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_71_6 ((uint8_t)0xc0) /* 71.6° */
1328 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_74_4 ((uint8_t)0xc8) /* 74.4° */
1329 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_77_0 ((uint8_t)0xd0) /* 77.0° */
1330 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_79_5 ((uint8_t)0xd8) /* 79.5° */
1331 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_81_9 ((uint8_t)0xe0) /* 81.9° */
1332 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_84_1 ((uint8_t)0xe8) /* 84.1° */
1333 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_86_2 ((uint8_t)0xf0) /* 86.2° */
1334 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_88_2 ((uint8_t)0xf8) /* 88.2° */
1335 #define FXLS896x_ORIENT_THS_REG_HYS_45_45 ((uint8_t)0x00) /* L-to-P 45° P-to-L 45° */
1336 #define FXLS896x_ORIENT_THS_REG_HYS_49_41 ((uint8_t)0x01) /* L-to-P 49° P-to-L 41° */
1337 #define FXLS896x_ORIENT_THS_REG_HYS_52_38 ((uint8_t)0x02) /* L-to-P 52° P-to-L 38° */
1338 #define FXLS896x_ORIENT_THS_REG_HYS_56_34 ((uint8_t)0x03) /* L-to-P 56° P-to-L 34° */
1339 #define FXLS896x_ORIENT_THS_REG_HYS_59_31 ((uint8_t)0x04) /* L-to-P 59° P-to-L 31° */
1340 #define FXLS896x_ORIENT_THS_REG_HYS_62_28 ((uint8_t)0x05) /* L-to-P 62° P-to-L 28° */
1341 #define FXLS896x_ORIENT_THS_REG_HYS_66_24 ((uint8_t)0x06) /* L-to-P 66° P-to-L 24° */
1342 #define FXLS896x_ORIENT_THS_REG_HYS_69_21 ((uint8_t)0x07) /* L-to-P 69° P-to-L 21° */
1343  /*------------------------------*/
1344 
1345 /*--------------------------------
1346 ** Register: SDCD_INT_SRC1
1347 ** Enum: FXLS896x_SDCD_INT_SRC1
1348 ** --
1349 ** Offset : 0x2D Sensor data change detection function 1.
1350 ** ------------------------------*/
1351 typedef union
1352 {
1353  struct
1354  {
1355  uint8_t z_ot_pol : 1; /* Z-axis outside of thresholds polarity flag. */
1356 
1357  uint8_t z_ot_ef : 1; /* Z-axis data or delta outside of upper and lower thresholds event flag. */
1358 
1359  uint8_t y_ot_pol : 1; /* Y-axis outside of thresholds polarity flag. */
1360 
1361  uint8_t y_ot_ef : 1; /* Y-axis data or delta outside of upper and lower thresholds event flag. */
1362 
1363  uint8_t x_ot_pol : 1; /* X-axis outside of thresholds polarity flag. */
1364 
1365  uint8_t x_ot_ef : 1; /* X-axis data or delta outside of upper and lower thresholds event flag. */
1366 
1367  uint8_t _reserved_ : 1;
1368  uint8_t ot_ea : 1; /* SDCD outside of thresholds event active flag. */
1369 
1370  } b;
1371  uint8_t w;
1372 } FXLS896x_SDCD_INT_SRC1_t;
1373 
1374 /*
1375 ** SDCD_INT_SRC1 - Bit field mask definitions
1376 */
1377 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_MASK ((uint8_t)0x01)
1378 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_SHIFT ((uint8_t)0)
1379 
1380 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_MASK ((uint8_t)0x02)
1381 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_SHIFT ((uint8_t)1)
1382 
1383 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_MASK ((uint8_t)0x04)
1384 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_SHIFT ((uint8_t)2)
1385 
1386 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_MASK ((uint8_t)0x08)
1387 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_SHIFT ((uint8_t)3)
1388 
1389 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_MASK ((uint8_t)0x10)
1390 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_SHIFT ((uint8_t)4)
1391 
1392 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_MASK ((uint8_t)0x20)
1393 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_SHIFT ((uint8_t)5)
1394 
1395 #define FXLS896x_SDCD_INT_SRC1_OT_EA_MASK ((uint8_t)0x80)
1396 #define FXLS896x_SDCD_INT_SRC1_OT_EA_SHIFT ((uint8_t)7)
1397 
1398 /*
1399 ** SDCD_INT_SRC1 - Bit field value definitions
1400 */
1401 #define FXLS896x_SDCD_INT_SRC1_OT_EA_INSIDE ((uint8_t)0x00) /* Event flag has not been asserted. */
1402 #define FXLS896x_SDCD_INT_SRC1_OT_EA_OUTSIDE ((uint8_t)0x80) /* Event flag has been asserted. */
1403 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1404 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_EVENT_YES ((uint8_t)0x20) /* Event has occured. */
1405 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1406 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_GT_THS ((uint8_t)0x10) /* Greater than upper threshold. */
1407 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1408 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_EVENT_YES ((uint8_t)0x08) /* Event has occured. */
1409 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1410 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_GT_THS ((uint8_t)0x04) /* Greater than upper threshold. */
1411 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1412 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_EVENT_YES ((uint8_t)0x02) /* Event has occured. */
1413 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1414 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_GT_THS ((uint8_t)0x01) /* Greater than upper threshold. */
1415  /*------------------------------*/
1416 
1417 /*--------------------------------
1418 ** Register: SDCD_INT_SRC2
1419 ** Enum: FXLS896x_SDCD_INT_SRC2
1420 ** --
1421 ** Offset : 0x2E Sensor data change detection function 2.
1422 ** ------------------------------*/
1423 typedef union
1424 {
1425  struct
1426  {
1427  uint8_t _reserved_ : 1;
1428  uint8_t z_wt_ef : 1; /* Z-axis data or delta inside of upper and lower thresholds event flag. */
1429 
1430  uint8_t _reserved_1 : 1;
1431  uint8_t y_wt_ef : 1; /* Y-axis data or delta inside of upper and lower thresholds event flag. */
1432 
1433  uint8_t _reserved_2 : 1;
1434  uint8_t x_wt_ef : 1; /* X-axis data or delta inside of upper and lower thresholds event flag. */
1435 
1436  uint8_t _reserved_3 : 1;
1437  uint8_t wt_ea : 1; /* SDCD within-thresholds event active flag. */
1438 
1439  } b;
1440  uint8_t w;
1441 } FXLS896x_SDCD_INT_SRC2_t;
1442 
1443 /*
1444 ** SDCD_INT_SRC2 - Bit field mask definitions
1445 */
1446 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_MASK ((uint8_t)0x02)
1447 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_SHIFT ((uint8_t)1)
1448 
1449 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_MASK ((uint8_t)0x08)
1450 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_SHIFT ((uint8_t)3)
1451 
1452 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_MASK ((uint8_t)0x20)
1453 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_SHIFT ((uint8_t)5)
1454 
1455 #define FXLS896x_SDCD_INT_SRC2_WT_EA_MASK ((uint8_t)0x80)
1456 #define FXLS896x_SDCD_INT_SRC2_WT_EA_SHIFT ((uint8_t)7)
1457 
1458 /*
1459 ** SDCD_INT_SRC2 - Bit field value definitions
1460 */
1461 #define FXLS896x_SDCD_INT_SRC2_WT_EA_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1462 #define FXLS896x_SDCD_INT_SRC2_WT_EA_EVENT_YES ((uint8_t)0x80) /* Event has occured. */
1463 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_IN_RANGE ((uint8_t)0x00) /* X-axis data or delta is >= SDCD_UTHS or =< */
1464  /* SDCD_LTHS values. */
1465 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_OUT_RANGE ((uint8_t)0x20) /* X-axis data or delta is < SDCD_UTHS and > */
1466  /* SDCD_LTHS value. */
1467 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_IN_RANGE ((uint8_t)0x00) /* Y-axis data or delta is >= SDCD_UTHS or =< */
1468  /* SDCD_LTHS values. */
1469 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_OUT_RANGE ((uint8_t)0x08) /* Y-axis data or delta is < SDCD_UTHS and > */
1470  /* SDCD_LTHS value. */
1471 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_IN_RANGE ((uint8_t)0x00) /* Z-axis data or delta is >= SDCD_UTHS or =< */
1472  /* SDCD_LTHS values. */
1473 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_OUT_RANGE ((uint8_t)0x02) /* Z-axis data or delta is < SDCD_UTHS and > */
1474  /* SDCD_LTHS value. */
1475  /*------------------------------*/
1476 
1477 /*--------------------------------
1478 ** Register: SDCD_CONFIG1
1479 ** Enum: FXLS896x_SDCD_CONFIG1
1480 ** --
1481 ** Offset : 0x2F Sensor data change detection function 1 register.
1482 ** ------------------------------*/
1483 typedef union
1484 {
1485  struct
1486  {
1487  uint8_t z_wt_en : 1; /* SDCD function Z-axis within thresholds condition enable. */
1488 
1489  uint8_t y_wt_en : 1; /* SDCD function Y-axis within thresholds condition enable. */
1490 
1491  uint8_t x_wt_en : 1; /* SDCD function X-axis within thresholds condition enable. */
1492 
1493  uint8_t z_ot_en : 1; /* SDCD function Z-axis outside of thresholds condition enable. */
1494 
1495  uint8_t y_ot_en : 1; /* SDCD function Y-axis outside of thresholds condition enable. */
1496 
1497  uint8_t x_ot_en : 1; /* SDCD function X-axis outside of thresholds condition enable. */
1498 
1499  uint8_t wt_ele : 1; /* SDCD within thresholds event latch enable. */
1500 
1501  uint8_t ot_ele : 1; /* SDCD outside of thresholds event latch enable. */
1502 
1503  } b;
1504  uint8_t w;
1505 } FXLS896x_SDCD_CONFIG1_t;
1506 
1507 /*
1508 ** SDCD_CONFIG1 - Bit field mask definitions
1509 */
1510 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_MASK ((uint8_t)0x01)
1511 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_SHIFT ((uint8_t)0)
1512 
1513 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_MASK ((uint8_t)0x02)
1514 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_SHIFT ((uint8_t)1)
1515 
1516 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_MASK ((uint8_t)0x04)
1517 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_SHIFT ((uint8_t)2)
1518 
1519 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_MASK ((uint8_t)0x08)
1520 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_SHIFT ((uint8_t)3)
1521 
1522 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_MASK ((uint8_t)0x10)
1523 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_SHIFT ((uint8_t)4)
1524 
1525 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_MASK ((uint8_t)0x20)
1526 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_SHIFT ((uint8_t)5)
1527 
1528 #define FXLS896x_SDCD_CONFIG1_WT_ELE_MASK ((uint8_t)0x40)
1529 #define FXLS896x_SDCD_CONFIG1_WT_ELE_SHIFT ((uint8_t)6)
1530 
1531 #define FXLS896x_SDCD_CONFIG1_OT_ELE_MASK ((uint8_t)0x80)
1532 #define FXLS896x_SDCD_CONFIG1_OT_ELE_SHIFT ((uint8_t)7)
1533 
1534 /*
1535 ** SDCD_CONFIG1 - Bit field value definitions
1536 */
1537 #define FXLS896x_SDCD_CONFIG1_OT_ELE_DIS ((uint8_t)0x00) /* Outside of thresholds event flag latching is */
1538  /* disabled. */
1539 #define FXLS896x_SDCD_CONFIG1_OT_ELE_EN ((uint8_t)0x80) /* Outside of thresholds event flag latching is */
1540  /* enabled. */
1541 #define FXLS896x_SDCD_CONFIG1_WT_ELE_DIS ((uint8_t)0x00) /* Within thresholds event flag latching is */
1542  /* disabled. */
1543 #define FXLS896x_SDCD_CONFIG1_WT_ELE_EN ((uint8_t)0x40) /* Within thresholds event flag latching is */
1544  /* enabled. */
1545 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */
1546  /* of thresholds condition evaluation. */
1547 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_EN ((uint8_t)0x20) /* X-axis data or delta is used in the outside of */
1548  /* thresholds condition evaluation. */
1549 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */
1550  /* of thresholds condition evaluation. */
1551 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_EN ((uint8_t)0x10) /* Y-axis data or delta is used in the outside of */
1552  /* thresholds condition evaluation. */
1553 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */
1554  /* of thresholds condition evaluation. */
1555 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_EN ((uint8_t)0x08) /* Z-axis data or delta is used in the outside of */
1556  /* thresholds condition evaluation. */
1557 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */
1558  /* of thresholds condition evaluation. */
1559 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_EN ((uint8_t)0x04) /* X-axis data or delta is used in the outside of */
1560  /* thresholds condition evaluation. */
1561 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */
1562  /* of thresholds condition evaluation. */
1563 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_EN ((uint8_t)0x02) /* Y-axis data or delta is used in the outside of */
1564  /* thresholds condition evaluation. */
1565 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */
1566  /* of thresholds condition evaluation. */
1567 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_EN ((uint8_t)0x01) /* Z-axis data or delta is used in the outside of */
1568  /* thresholds condition evaluation. */
1569  /*------------------------------*/
1570 
1571 /*--------------------------------
1572 ** Register: SDCD_CONFIG2
1573 ** Enum: FXLS896x_SDCD_CONFIG2
1574 ** --
1575 ** Offset : 0x30 Sensor data change detection function 2 register.
1576 ** ------------------------------*/
1577 typedef union
1578 {
1579  struct
1580  {
1581  uint8_t ref_upd : 1; /* SDCD synchronous X/Y/Z reference values update bit. */
1582 
1583  uint8_t mode : 1; /* SDCD input data mode. */
1584 
1585  uint8_t wt_log_sel : 1; /* SDCD within thresholds event logic selection. */
1586 
1587  uint8_t wt_dbctm : 1; /* SDCD within thresholds event debounce counter behavior. */
1588 
1589  uint8_t ot_dbctm : 1; /* SDCD outside of threshold event debounce counter behavior. */
1590 
1591  uint8_t ref_updm : 2; /* SDCD internal reference values update mode. */
1592 
1593  uint8_t sdcd_en : 1; /* SDCD function. */
1594 
1595  } b;
1596  uint8_t w;
1597 } FXLS896x_SDCD_CONFIG2_t;
1598 
1599 /*
1600 ** SDCD_CONFIG2 - Bit field mask definitions
1601 */
1602 #define FXLS896x_SDCD_CONFIG2_REF_UPD_MASK ((uint8_t)0x01)
1603 #define FXLS896x_SDCD_CONFIG2_REF_UPD_SHIFT ((uint8_t)0)
1604 
1605 #define FXLS896x_SDCD_CONFIG2_MODE_MASK ((uint8_t)0x02)
1606 #define FXLS896x_SDCD_CONFIG2_MODE_SHIFT ((uint8_t)1)
1607 
1608 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_MASK ((uint8_t)0x04)
1609 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_SHIFT ((uint8_t)2)
1610 
1611 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_MASK ((uint8_t)0x08)
1612 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_SHIFT ((uint8_t)3)
1613 
1614 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_MASK ((uint8_t)0x10)
1615 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_SHIFT ((uint8_t)4)
1616 
1617 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_MASK ((uint8_t)0x60)
1618 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_SHIFT ((uint8_t)5)
1619 
1620 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_MASK ((uint8_t)0x80)
1621 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_SHIFT ((uint8_t)7)
1622 
1623 /*
1624 ** SDCD_CONFIG2 - Bit field value definitions
1625 */
1626 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_DIS ((uint8_t)0x00) /* SDCD function is disabled. */
1627 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_EN ((uint8_t)0x80) /* SDCD function is Enabled. */
1628 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_12_BIT ((uint8_t)0x00) /* The function stores the first 12-bit X/Y/Z */
1629  /* decimated and trimmed input data. */
1630 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_FIRST ((uint8_t)0x20) /* The function stores the first decimated and */
1631  /* trimmed X/Y/Z acceleration input data. */
1632 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_SDCD_REF ((uint8_t)0x40) /* The function updates the SDCD_REF_X/Y/Z values */
1633  /* with the current decimated and trimmed X/Y/Z */
1634  /* acceleration input data after the function */
1635  /* evaluation. */
1636 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_FIXED_VAL ((uint8_t)0x60) /* The function uses a fixed value of 0 for each */
1637 /* of the SDCD_REF_X/Y/Z registers. */
1638 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */
1639 /* current outside of thresholds result for the */
1640 /* enabled axes is false. */
1641 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_CLEARED ((uint8_t)0x10) /* Debounce counter is cleared whenever the */
1642  /* current outside of thresholds result for the */
1643  /* enabled axes is false. */
1644 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */
1645 /* current outside of thresholds result for the */
1646 /* enabled axes is false. */
1647 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_CLEARED ((uint8_t)0x08) /* Debounce counter is cleared whenever the */
1648  /* current outside of thresholds result for the */
1649  /* enabled axes is false. */
1650 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_AND ((uint8_t)0x00) /* Function uses the logical AND of the enabled */
1651  /* axes. */
1652 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_OR ((uint8_t)0x04) /* Function uses the logical OR of the enabled */
1653  /* axes. */
1654 #define FXLS896x_SDCD_CONFIG2_MODE_XYZ ((uint8_t)0x00) /* Function uses X, Y, Z acceleration data for the */
1655  /* window comparison. */
1656 #define FXLS896x_SDCD_CONFIG2_MODE_VECM ((uint8_t)0x02) /* Function uses Vector magnitude data for the */
1657  /* window comparison on the X-axis channel only. */
1658 #define FXLS896x_SDCD_CONFIG2_REF_UPD_NO_PENDING \
1659  ((uint8_t)0x00) /* No reference update pending or reference update \ \ \
1660  */
1661 /* has completed. */
1662 #define FXLS896x_SDCD_CONFIG2_REF_UPD_SYNC_UPDATE ((uint8_t)0x01) /* Triggers a synchronous update of the internal */
1663  /* X/Y/Z reference registers. */
1664  /*------------------------------*/
1665 
1666 /*--------------------------------
1667 ** Register: SDCD_OT_DBCNT
1668 ** Enum: FXLS896x_SDCD_OT_DBCNT
1669 ** --
1670 ** Offset : 0x31 Sensor Data Change Detection outside of thresholds condition debounce count value.
1671 ** ------------------------------*/
1672 typedef uint8_t FXLS896x_SDCD_OT_DBCNT_t;
1673 
1674 /*--------------------------------
1675 ** Register: SDCD_WT_DBCNT
1676 ** Enum: FXLS896x_SDCD_WT_DBCNT
1677 ** --
1678 ** Offset : 0x32 Sensor Data Change Detection within thresholds condition debounce count value.
1679 ** ------------------------------*/
1680 typedef uint8_t FXLS896x_SDCD_WT_DBCNT_t;
1681 
1682 /*--------------------------------
1683 ** Register: SDCD_LTHS_LSB
1684 ** Enum: FXLS896x_SDCD_LTHS_LSB
1685 ** --
1686 ** Offset : 0x33 Sensor Data Change Detection lower threshold value LSB.
1687 ** ------------------------------*/
1688 typedef uint8_t FXLS896x_SDCD_LTHS_LSB_t;
1689 
1690 /*--------------------------------
1691 ** Register: SDCD_LTHS_MSB
1692 ** Enum: FXLS896x_SDCD_LTHS_MSB
1693 ** --
1694 ** Offset : 0x34 Sensor Data change Detection lower threshold value MSB.
1695 ** ------------------------------*/
1696 typedef uint8_t FXLS896x_SDCD_LTHS_MSB_t;
1697 
1698 /*--------------------------------
1699 ** Register: SDCD_UTHS_LSB
1700 ** Enum: FXLS896x_SDCD_UTHS_LSB
1701 ** --
1702 ** Offset : 0x35 Sensor Data change detection upper threshold value LSB.
1703 ** ------------------------------*/
1704 typedef uint8_t FXLS896x_SDCD_UTHS_LSB_t;
1705 
1706 /*--------------------------------
1707 ** Register: SDCD_UTHS_MSB
1708 ** Enum: FXLS896x_SDCD_UTHS_MSB
1709 ** --
1710 ** Offset : 0x36 Sensor Data change detection upper threshold value MSB.
1711 ** ------------------------------*/
1712 typedef uint8_t FXLS896x_SDCD_UTHS_MSB_t;
1713 
1714 
1715 /*--------------------------------
1716 ** Register: SELF_TEST_CONFIG1
1717 ** Enum: FXLS896x_SELF_TEST_CONFIG1
1718 ** --
1719 ** Offset : 0x37 Self Test Configuration function 1 register.
1720 ** ------------------------------*/
1721 typedef union
1722 {
1723  struct
1724  {
1725  uint8_t st_idle : 5; /* Self-Test Idle phase duration. */
1726 
1727  } b;
1728  uint8_t w;
1729 } FXLS896x_SELF_TEST_CONFIG1_t;
1730 
1731 /*
1732 ** SELF_TEST_CONFIG1 - Bit field mask definitions
1733 */
1734 #define FXLS896x_SELF_TEST_CONFIG1_ST_IDLE_MASK ((uint8_t)0x1f)
1735 #define FXLS896x_SELF_TEST_CONFIG1_ST_IDLE_SHIFT ((uint8_t)0)
1736 
1737 
1738 /*--------------------------------
1739 ** Register: SELF_TEST_CONFIG2
1740 ** Enum: FXLS896x_SELF_TEST_CONFIG2
1741 ** --
1742 ** Offset : 0x38 Self Test Configuration function 2 register.
1743 ** ------------------------------*/
1744 typedef union
1745 {
1746  struct
1747  {
1748  uint8_t st_dec : 4; /* Self-Test measurement phase decimation factor. */
1749 
1750  } b;
1751  uint8_t w;
1752 } FXLS896x_SELF_TEST_CONFIG2_t;
1753 
1754 /*
1755 ** SELF_TEST_CONFIG2 - Bit field mask definitions
1756 */
1757 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_MASK ((uint8_t)0x0f)
1758 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_SHIFT ((uint8_t)0)
1759 
1760 /*
1761 ** SELF_TEST_CONFIG2 - Bit field value definitions
1762 */
1763 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_1 ((uint8_t)0x00)
1764 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_2 ((uint8_t)0x01)
1765 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_4 ((uint8_t)0x02)
1766 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_8 ((uint8_t)0x03)
1767 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_16 ((uint8_t)0x04)
1768 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_32 ((uint8_t)0x05)
1769 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_64 ((uint8_t)0x06)
1770 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_128 ((uint8_t)0x07)
1771 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_256 ((uint8_t)0x08)
1772 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_512 ((uint8_t)0x09)
1773 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_1024 ((uint8_t)0x0a)
1774 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_2048 ((uint8_t)0x0b)
1775 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_4096 ((uint8_t)0x0c)
1776 
1777 
1778 #endif /* FXLS896X_H_ */
FXLS896x_TEMP_OUT_t
uint8_t FXLS896x_TEMP_OUT_t
Definition: fxls896x.h:157
FXLS896x_OFF_Y_t
uint8_t FXLS896x_OFF_Y_t
Definition: fxls896x.h:987
FXLS896x_SDCD_OT_DBCNT_t
uint8_t FXLS896x_SDCD_OT_DBCNT_t
Definition: fxls896x.h:1672
FXLS896x_BUF_Y_MSB_t
uint8_t FXLS896x_BUF_Y_MSB_t
Definition: fxls896x.h:289
FXLS896x_OUT_Y_LSB_t
uint8_t FXLS896x_OUT_Y_LSB_t
Definition: fxls896x.h:197
FXLS896x_INT_EN_t::sdcd_wt_en
uint8_t sdcd_wt_en
Definition: fxls896x.h:814
FXLS896x_BUF_X_MSB_t
uint8_t FXLS896x_BUF_X_MSB_t
Definition: fxls896x.h:271
FXLS896x_SYS_MODE_t::buf_gate_cnt
uint8_t buf_gate_cnt
Definition: fxls896x.h:358
FXLS896x_ORIENT_DBCOUNT_t
uint8_t FXLS896x_ORIENT_DBCOUNT_t
Definition: fxls896x.h:1214
FXLS896x_INT_EN_t::drdy_en
uint8_t drdy_en
Definition: fxls896x.h:819
FXLS896x_WAKE_IDLE_LSB_t
uint8_t FXLS896x_WAKE_IDLE_LSB_t
Definition: fxls896x.h:754
FXLS896x_OUT_X_MSB_t
uint8_t FXLS896x_OUT_X_MSB_t
Definition: fxls896x.h:189
FXLS896x_OFF_Z_t
uint8_t FXLS896x_OFF_Z_t
Definition: fxls896x.h:995
FXLS896x_SLEEP_IDLE_LSB_t
uint8_t FXLS896x_SLEEP_IDLE_LSB_t
Definition: fxls896x.h:770
FXLS896x_OFF_X_t
uint8_t FXLS896x_OFF_X_t
Definition: fxls896x.h:979
FXLS896x_ASLP_COUNT_MSB_t
uint8_t FXLS896x_ASLP_COUNT_MSB_t
Definition: fxls896x.h:794
FXLS896x_BUF_Z_LSB_t
uint8_t FXLS896x_BUF_Z_LSB_t
Definition: fxls896x.h:298
FXLS896x_SLEEP_IDLE_MSB_t
uint8_t FXLS896x_SLEEP_IDLE_MSB_t
Definition: fxls896x.h:778
FXLS896x_VECM_LSB_t
uint8_t FXLS896x_VECM_LSB_t
Definition: fxls896x.h:165
FXLS896x_OUT_Y_MSB_t
uint8_t FXLS896x_OUT_Y_MSB_t
Definition: fxls896x.h:205
FXLS896x_INT_EN_t::orient_en
uint8_t orient_en
Definition: fxls896x.h:812
FXLS896x_VECM_MSB_t
uint8_t FXLS896x_VECM_MSB_t
Definition: fxls896x.h:173
FXLS896x_SYS_MODE_t::buf_gate_error
uint8_t buf_gate_error
Definition: fxls896x.h:360
FXLS896x_SDCD_LTHS_MSB_t
uint8_t FXLS896x_SDCD_LTHS_MSB_t
Definition: fxls896x.h:1696
FXLS896x_INT_EN_t::sdcd_ot_en
uint8_t sdcd_ot_en
Definition: fxls896x.h:816
FXLS896x_PROD_REV_t::prod_rev_maj
uint8_t prod_rev_maj
Definition: fxls896x.h:322
FXLS896x_PROD_REV_t::prod_rev_min
uint8_t prod_rev_min
Definition: fxls896x.h:319
FXLS896x_BUF_Z_MSB_t
uint8_t FXLS896x_BUF_Z_MSB_t
Definition: fxls896x.h:307
FXLS896x_OUT_Z_MSB_t
uint8_t FXLS896x_OUT_Z_MSB_t
Definition: fxls896x.h:221
FXLS896x_OUT_Z_LSB_t
uint8_t FXLS896x_OUT_Z_LSB_t
Definition: fxls896x.h:213
FXLS896x_ASLP_COUNT_LSB_t
uint8_t FXLS896x_ASLP_COUNT_LSB_t
Definition: fxls896x.h:786
FXLS896x_WHO_AM_I_t
uint8_t FXLS896x_WHO_AM_I_t
Definition: fxls896x.h:344
FXLS896x_INT_EN_t::boot_dis
uint8_t boot_dis
Definition: fxls896x.h:808
FXLS896x_SDCD_WT_DBCNT_t
uint8_t FXLS896x_SDCD_WT_DBCNT_t
Definition: fxls896x.h:1680
FXLS896x_INT_EN_t::buf_en
uint8_t buf_en
Definition: fxls896x.h:818
FXLS896x_INT_EN_t::wake_out_en
uint8_t wake_out_en
Definition: fxls896x.h:806
FXLS896x_SDCD_UTHS_MSB_t
uint8_t FXLS896x_SDCD_UTHS_MSB_t
Definition: fxls896x.h:1712
FXLS896x_INT_EN_t::aslp_en
uint8_t aslp_en
Definition: fxls896x.h:810
FXLS896x_BUF_Y_LSB_t
uint8_t FXLS896x_BUF_Y_LSB_t
Definition: fxls896x.h:280
FXLS896x_OUT_X_LSB_t
uint8_t FXLS896x_OUT_X_LSB_t
Definition: fxls896x.h:181
FXLS896x_BUF_X_LSB_t
uint8_t FXLS896x_BUF_X_LSB_t
Definition: fxls896x.h:262
FXLS896x_SDCD_UTHS_LSB_t
uint8_t FXLS896x_SDCD_UTHS_LSB_t
Definition: fxls896x.h:1704
FXLS896x_WAKE_IDLE_MSB_t
uint8_t FXLS896x_WAKE_IDLE_MSB_t
Definition: fxls896x.h:762
FXLS896x_SDCD_LTHS_LSB_t
uint8_t FXLS896x_SDCD_LTHS_LSB_t
Definition: fxls896x.h:1688
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